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Title:
PSK DEMODULATOR
Document Type and Number:
Japanese Patent JPS6018047
Kind Code:
A
Abstract:

PURPOSE: To eliminate the need for synchronization as well as the inconvenience due to a delay line by dividing a PSK modulation signal into two signals having a 90° phase difference and delivering 0 or 1 after deciding whether the component of each signal is higher or lower than the threshold value.

CONSTITUTION: The 1st reference signal of the same frequency as the carrier wave frequency given from a reference oscillator 18 is supplied to a mixer 16. While the 2nd reference signal obtained via a 90° phase shifter 19 is supplied to a mixer 17. Then mixers 16 and 17 multiply the input signal by the 1st and 2nd reference signals and extract the 1st and 2nd low band pass components to supply them to the integrating and damping deices 20 and 21 as well as sampling circuits 22 and 23 respectively. The output of the circuit 23 is compared with the positive and negative threshold values by analog comparators 33 and 34 and then supplied to a register 37. The output of the circuit 23 is also compared by analog comparators 35 and 36 in the same way and supplied to the register 37. The output of the register 37 is supplied to a digital comparator 39 and compared with the information preceding by a symbol and stored in a memory 38.


Inventors:
TSUCHIYA MASAHIRO
HAMATSU MASAHIRO
Application Number:
JP12557383A
Publication Date:
January 30, 1985
Filing Date:
July 12, 1983
Export Citation:
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Assignee:
CLARION CO LTD
International Classes:
H04L27/22; H04L27/00; H04L27/18; (IPC1-7): H04L27/22
Domestic Patent References:
JPS55107367A1980-08-18
Attorney, Agent or Firm:
Takesaburo Nagata