PURPOSE: To supply a control signal whose delay time is set to a necessary minimum, to a switching element, by using an (n) stage shift register, and forming an on-control signal to an off-control signal by delaying it by a constant interval of time.

CONSTITUTION: When an original signal is applied to an input point (a) of an (n) stage shift register 31, and a clock pulse having sufficiently high frequency and high accuracy, comparing with the original signal is applied to a point (g), the original signal is delayed by time td of (n) times of the clock period, and is outputted to an output terminal (b). A signal from the point (a) and a signal of the point (b), and signals which have inverted the signals from the point (a) and the point (b) by invertor gates 32, 33 are converted to AND signals by an AND gate 34 and an AND gate 35, respectively, and become outputs (e), (f) having a rise delay time td in which a rise time point of one signal is equal to (n) times of the clock pulse period, to a fall time point of the other signal.