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Title:
MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS60123062
Kind Code:
A
Abstract:

PURPOSE: To shorten diffusion time, and to improve the degree of integration by forming a collector wall region by diffusion from upper and lower sections in the same manner as the formation of an isolation region.

CONSTITUTION: Antimony or arsenic is doped selectively into a P type Si substrate 1 to form an N type collector buried layer 2. An oxide film is removed selectively, boron is doped into the exposed P type Si substrate 1 to shape P type buried layers 3 for isolation, and phosphorus is doped selectively into the collector buried layer 2 to form a buried layer 12 for a collector wall. An N type high-resistance Si layer 13 is grown in an epitaxial manner, and an N type low-resistance Si layer 14 is grown on the Si layer 13. Upper isolation layers 5 are shaped, an upper collector wall layer 15 is formed, and the whole is thermally treated for drive-in. A base region 7, the front of diffusion thereof is formed in the low-resistance Si layer 14 as an upper layer and the greater part of a depletion layer thereof can be spread to the high-resistance Si layer 13 as a lower layer, is formed.


Inventors:
AOKI KUNIO
Application Number:
JP23175583A
Publication Date:
July 01, 1985
Filing Date:
December 08, 1983
Export Citation:
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Assignee:
MATSUSHITA ELECTRONICS CORP
International Classes:
H01L21/74; H01L21/331; H01L29/72; H01L29/73; H01L29/732; (IPC1-7): H01L21/74
Domestic Patent References:
JPS58115856A1983-07-09
JPS55111156A1980-08-27
JPS54126478A1979-10-01
Attorney, Agent or Firm:
Akira Kobiji (2 outside)



 
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