Title:
ADDRESS CONTROLLING CIRCUIT
Document Type and Number:
Japanese Patent JPS5922165
Kind Code:
A
Abstract:
PURPOSE:To perform the parallel pipeline processing of address control and arithmetic by providing two counters, three registers, two selectors, shifting circuit, adder, AND circuit, and control circuit for controlling respective parts. CONSTITUTION:A selecting circuit 51 selects one of counters 47 and 48 and a register (RG) 49, and its output is supplied to one terminal of the adder 54 through the shifting circuit 52. A selecting circuit 53 selects one of a counters 48, RGs 49 and 50, and an RG56 as the address register of a memory, and its output is supplied to the other input terminal of the adder 54. The output of the adder 54 is ANDed with the contents of the RG50 by the AND circuit 55 on bit correspondence basis, and the result is set in the RG56. Controlling circuits 57 and 58 reset or increase the contents of the counters 47 and 48 according to the mode, function to control the operation of the circuits 51 and 53 and the number of shifting of the circuit 51 and to reset the RG56, and perform systematic address control necessary for various kinds of high-level arithmetic processing. Consequently, the circuit scale is reduced and LSI-implementation is possible.
Inventors:
KANEKO TAKAO
YAMAUCHI HIROKI
IWATA ATSUSHI
YAMAUCHI HIROKI
IWATA ATSUSHI
Application Number:
JP13158982A
Publication Date:
February 04, 1984
Filing Date:
July 28, 1982
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G06F12/02; G06F17/14; G11C8/04; (IPC1-7): G06F13/00
Domestic Patent References:
| JPS509344A | 1975-01-30 |
Attorney, Agent or Firm:
Makoto Suzuki