PURPOSE: To prevent the processing speed from lowering by only adding a small amount of hardware, by controlling the transfer/blocking of a basic clock at the time of refreshing with a microprogram.

CONSTITUTION: The output of a flip-flop 9 is supplied to a basic clock controlling circuit 10 and the basic clock controlling circuit 10 supplies a synchronizing clock to a microsequencer 7, instruction register and decoder 8, ALU4 and DRAM1 by obtaining a basic clock outputted from a clock generator 11 and changing the phase. The output of a refresh timing generating circuit 12 is also supplied to the basic clock controlling device 10 and the controlling device 10 also performs transfer control (generation/stoppage) of the basic clock based on the content of the flip-flop 9 at the time of refresh cycle. The refresh timing generating circuit 12 outputs a refresh cycle signal synchronously to the basic clock outputted from the clock generator 11.