Title:
SCRAMBLER ENCODER INTEGRATED AND USING QUASI-RANDOM SEQUENCE GENERATOR
Document Type and Number:
Japanese Patent JPS5936454
Kind Code:
A
Abstract:
Simplified apparatus for performing integrated scrambling and encoding or descrambling and decoding of block code digital transmissions is disclosed. The system involves setting the scrambling length equal to an integer multiple of the block length, and then implementing a pseudorandom number sequence generator within the block length counter. The output of the pseudorandom number sequence generator is then logically combined with the incoming data to provide scrambled data, simplifying the complexity of the encoder or decoder significantly.
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Inventors:
EDOWAADO JIEI UERUDON JIYUNIA
Application Number:
JP8245383A
Publication Date:
February 28, 1984
Filing Date:
May 11, 1983
Export Citation:
Assignee:
TANDAMU COMPUTER ZU INC
International Classes:
G06F11/10; H04L25/03; H03M13/00; (IPC1-7): H04L1/10
Domestic Patent References:
| JPS50143456A | 1975-11-18 | |||
| JPS5525291A | 1980-02-22 |
Attorney, Agent or Firm:
Minoru Nakamura