Title:
HYBRID ANALOG-DIGITAL INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5821857
Kind Code:
A
Abstract:
PURPOSE: To prevent a noise generated from a digital circuit from being transmitted to an analog circuit by insulating and isolating a semiconductor substrate of the analog circuit from a semiconductor substrate of a digital circuit via a P-N junction biased reversely.
CONSTITUTION: A digital circuit 214 is constructed of N-channel MOS transistors 209 all formed in a P-type well 202. This well is reversely biased from an N-type substrate. Accordingly, the noise produced from the circuit 214 is stopped by the P-N junction, and is not almost transmitted out of the well. In this manner, an analog circuit 213 is operated not by being affected by the noise of the circuit 214.
Inventors:
OOSHIMA HIROYUKI
Application Number:
JP12111581A
Publication Date:
February 08, 1983
Filing Date:
July 31, 1981
Export Citation:
Assignee:
SUWA SEIKOSHA KK
International Classes:
H01L21/8238; H01L27/092; H01L29/78; H01L27/02; (IPC1-7): H01L27/08; H01L29/78
Attorney, Agent or Firm:
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