PURPOSE: To reduce spreading resistance, and to enable to reduce extremely source resistance of a field effect transistor device by a method wherein source and drain electrodes are formed according to the selfalignment method on the sides of the mesa part of a semiconductor active layer under a gate electrode.

CONSTITUTION: An N type semiconductor layer 2 is formed by implanting silicon ions in a semiinsulating gallium arsenide substrate 1, and an aluminum Schottky barrier gate electrode 5 is formed on the surface. The whole surface is covered with a silicon oxide film 8, and anisotropic etching is performed to remove the SiO2 film leaving the SiO2 side wall parts 8'. The semiconductor layer 2 is anisotropically etched to leave only the gate part semiconductor layer 2', a gold- germanium alloy and a nickel film 9 are adhered on the whole surface, etching is performed to expose the heads of the gate electrode 5 and the SiO2 side wall parts 8', alloying of the gold-germanium alloy, the nickel film 9 and GaAs is performed, and source and drain electrodes are formed at the mesa parts of the semiconductor layer 2.