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Title:
HYBRID INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPS59188156
Kind Code:
A
Abstract:

PURPOSE: To increase the integration and to reduce the size of a hybrid integrated circuit device by printing the second conductor layer having a wire bonding pad on an unbaked dielectric layer, thereby preventing the ooze at the printing time and narrowing the interval between the printing layers.

CONSTITUTION: A Pd-Ag paste is printed on a ceramic substrate 1, and the first conductor layer 2 made of an external lead teminal 3, a resistance terminal 4 and a wiring layer 5, etc. is formed. A resistance layer 11 is formed between the terminals 4, dielectric paste made of glass is printed to form a dielectric layer 7. The Pa-Ag past is printed to form the second conductor layer 8. Unbaked dielectric layer 7 instantaneously absorbs the moisture in the paste at the printing time so that no ooze occurs. Accordingly, the interval between the second conductor layers 8 on the layer 7 can be narrowed. The layer 8 becomes the wiring layer 15 having a wire bonding pad 9 around an IC chip 6, and an IC chip plating portion becomes a metallized layer 17. The layers 8, 7 are simultaneously baked.


Inventors:
IGARASHI TOORU
ENDOU TSUNEO
Application Number:
JP6089083A
Publication Date:
October 25, 1984
Filing Date:
April 08, 1983
Export Citation:
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Assignee:
HITACHI IRUMA DENSHI KK
HITACHI LTD
International Classes:
H05K3/46; H01L21/60; H01L25/16; (IPC1-7): H01L23/48; H01L27/13; H05K1/02
Attorney, Agent or Firm:
Akio Takahashi



 
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