PURPOSE: To obtain a FET having recess structure having small source and drain resistance and uniform threshold voltage by forming N+ layers to source and drain sections and forming structure in which a gate forming section is dug in.

CONSTITUTION: An SiO2 layer 15 with a gate opening 21 and an silicon nitride layer 31 are shaped on a semi-insulating GaAs substrate 11, and a CVD-SiO2 film 32 is further applied and Sn is diffused into the SiO2 layer 15 through heat treatment to form N+ layers 14. The SiO2 film 32 is removed. A dug-in section 33 is formed to the GaAs substrate 11 while using the SiO2 layer 15 as a mask, the SiO2 layer 15 is side-etched in the same extent as the depth of the dug-in section 33, and ions are implanted to the gate opening section 21 to shape an N type operating layer 12. A gate metal 35 is applied, and the SiO2 layer 15 is removed through etching, and a gate electrode 36 and source and drain electrodes 16, 17 are formed.