Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
FAULT SIMULATION SYSTEM
Document Type and Number:
Japanese Patent JPH04118780
Kind Code:
A
Abstract:

PURPOSE: To execute the fault simulation of a large scale circuit by holding only connection information with respect the partial circuit of a part for which processor takes charge.

CONSTITUTION: A fault defined at a circuit that becomes the target of simulation is dissolved to (n) (m>n>1) exclusive fault partial sets, and (m) processors 2 are divided into (m) processor groups at every (k) (n*k=m) units, and one fault partial set is allocated to every processor group. In each processor group, the circuit that becomes the target of the simulation is divided into (k) partial circuits, and the partial circuit allocated to every processor, and simultaneous fault simulation with respect to the allocated partial set of the fault is executed based on the division of the circuit in the processor group. In such a way, it is possible to execute the simulation by holding only the connection information with respect to the partial circuit of the circuit for which each processor takes charge, which enables the fault simulation of the large scale circuit to be performed.


Inventors:
NAKADA TOSHIYUKI
Application Number:
JP23877890A
Publication Date:
April 20, 1992
Filing Date:
September 07, 1990
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
G06F11/26; G06F15/16; G06F17/50; (IPC1-7): G06F11/26; G06F15/16; G06F15/60
Attorney, Agent or Firm:
Shinsuke Honjo



 
Previous Patent: 軸流タービン

Next Patent: IMAGE GENERATING SYSTEM