SEMICONDUCTOR MEMORY HAVING DEFECT REMEDYING CIRCUIT

Title:

SEMICONDUCTOR MEMORY HAVING DEFECT REMEDYING CIRCUIT

Document Type and Number:

Japanese Patent JPS6120300

Kind Code:

A

Abstract:

PURPOSE: To make a small number of defective chips conforming products and improve yield by introducing defect remedying in a memory that makes reading and writing of data serially.

CONSTITUTION: The memory is provided with word lines W0WWM-1 of M=2m, data lines D0WDN-1 of N=2n and MN memory cells MC00WMCN-1,N-1. Any one of word lines can be selected by a decoder 2. However, data lines are selected serially by a data line selecting circuit 4 in order of D0, D1...DN-1. Two spare data lines SD0, SD1 are provided, and used as reserves when one of regular data lines D0WDN-1 becomes defective. A counter 10, ROMs 20, 21, comparators 30, 31 and a switching circuit 40 are provided to switch regular data lines and spare data lines. As there are two spare data lines, two ROMs and compara tors are provided.

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Inventors:

HORIGUCHI SHINJI
SHIMOHIGASHI KATSUHIRO
AOKI MASAKAZU
NAKAGOME YOSHINOBU
IKENAGA SHINICHI

Application Number:

JP14051184A

Publication Date:

January 29, 1986

Filing Date:

July 09, 1984

Export Citation:

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Assignee:

HITACHI LTD

International Classes:

G11C29/00; G11C19/00; G11C29/04; H01L21/82; H01L27/10; (IPC1-7): G11C19/00; G11C29/00; H01L21/82; H01L27/10

Attorney, Agent or Firm:

Katsuo Ogawa (1 person outside)

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