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Title:
PREPARATION OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS58176974
Kind Code:
A
Abstract:

PURPOSE: To obtain a MOS semiconductor element having stabilized gate dielectric strength by forming two-level or three-level silicon gate electrodes with different deposition methods.

CONSTITUTION: A gate insulating film 2 consisting of a SiO2 film on a field insulating film 4 deposited over a semiconductor substrate 1, a polycrystalline silicon film 5 is deposited thereon by the vacuum deposition method, and moreover a polycrystalline silicon film is deposited thereon by the CVD method. Thereafter, such film is patterned by the photo processing and a gate electrode and gate insulating film 2 consisting of two-level polycrystalline silicon films 5, 6 are formed by the dry etching method. In succession, source and drain are formed by well known method and a MOS semiconductor element can be obtained. When such two-level polycrystalline silicon film is formed, since a polycrystalline silicon film 5 formed as the under layer is deposited, a gate dielectric strength is not deteriorated, and since the uppermost polycrystalline silicon film 6 is deposited by the CVD method, invasion of chemical solution is rejected through a dense film and thereby a gate insulating film can be kept stable.


Inventors:
TANAKA SHINPEI
Application Number:
JP5989682A
Publication Date:
October 17, 1983
Filing Date:
April 09, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L29/423; H01L29/43; H01L29/49; H01L29/78; (IPC1-7): H01L29/62
Attorney, Agent or Firm:
Koshiro Matsuoka



 
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