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Title:
LATERAL BI-POLAR TRANSISTOR
Document Type and Number:
Japanese Patent JPS596573
Kind Code:
A
Abstract:

PURPOSE: To obtain a high density bi-polar transistor which can maintain high hFE even in the region of large quantity of current by a method wherein the distances between opposed surfaces of emitter and collector regions have parts different according to places, and both the regions are formed at the same time.

CONSTITUTION: An emitter region 11 and a collector region 13 are formed at the same time, and the base width is dominantly determined by the clearance 12 between the emitter region 11 and the collector region 13. When the base widths on a mask pattern are: a=4μm, b=d=5μm and c=6μm respectively, the rate of current amplification is improved in the region of large emitter current over 100μA, and then the rate of improvement ranges over 100% at the time of 500μA. This is due to the fact that the narrow base width of 4μm acts on the mask pattern and thus offers high hFE in case of small emitter current, and that the wide base width acts accompanied with the increase of current, resulting in the prevention of sudden decrease of hFE.


Inventors:
HIROFUJI HIROICHI
Application Number:
JP11572982A
Publication Date:
January 13, 1984
Filing Date:
July 02, 1982
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L29/73; H01L21/331; H01L29/72; (IPC1-7): H01L29/72
Domestic Patent References:
JPS55165674A1980-12-24
JPS55156361A1980-12-05
JPS5029172A1975-03-25
Attorney, Agent or Firm:
Akira Kobiji (2 outside)



 
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