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Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTING MEANS
Document Type and Number:
Japanese Patent JPS6011952
Kind Code:
A
Abstract:

PURPOSE: To simplify a data path system by using a universal shift register to form a chekcing data path system.

CONSTITUTION: When the writing is performed with a memory part 1, the store data of the controller side 200 is written with no intervention of a syndrome generator 2. While the fetch data read out of the part 1 is transferred to the controller side 200 with no intervention of a checker collector 3. In a check mode of the generator 2, both the store data and an error correction code are transferred to the side 200 with no intervention of the part 1. In a checking mode of the collector 3, the store data undergoes a correction of errors via a parallel/serial register 7 and universal shift register 5 and 6 and is transferred to the controller side 200.


Inventors:
NAITOU AKIRA
SHIRAKAWA TADAFUMI
Application Number:
JP11969183A
Publication Date:
January 22, 1985
Filing Date:
July 01, 1983
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G06F11/10; G06F12/16; G11C29/00; G11C29/42; (IPC1-7): G06F12/16; G06F11/10; G11C29/00
Domestic Patent References:
JPS5693192A1981-07-28
JPS5693196A1981-07-28
JPS5730196A1982-02-18
Attorney, Agent or Firm:
Masuo Oiwa