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Patent Searching and Data


Title:
VARIABLE DELAY CIRCUIT
Document Type and Number:
Japanese Patent JPS5922436
Kind Code:
A
Abstract:

PURPOSE: To attain high accuracy and high stability, by eliminating the difference in delay time by using a differential circuit for a driving circuit, taking balance between the rising and falling times and avoiding the change in pulse width even if the delay time is large.

CONSTITUTION: The driving circuit 11 is a bipolar circuit and a CR circuit comprising a resistor 12 and a varactor diode 13 is formed to each output. A bipolar signal from each CR circuit is inputted to a differential input type receiving circuit 11' of the next stage to perform waveform shaping. A voltage applied to the varactor diode 13 is given via a DA converter 14. The delay time is changed by changing an input D of the DA converter. When a reverse bias voltage is small and the capacitance is large, even if the waveform at points A and B is different between the rising and falling times since the receiving circuit 11' is formed as a differential input, no difference in the increment of delay time is produced between the rising and the falling times at outputs O1 and O2.


Inventors:
YAMAGIWA AKIRA
MATSUMOTO TAKASHI
Application Number:
JP13031482A
Publication Date:
February 04, 1984
Filing Date:
July 28, 1982
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03K5/13; (IPC1-7): H03K5/13
Domestic Patent References:
JP53114949B
JPS5757642B21982-12-06
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)