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Title:
PHOTOMASK
Document Type and Number:
Japanese Patent JPS5960439
Kind Code:
A
Abstract:

PURPOSE: To reduce the number of manufacturing steps of a photomask, to short en the manufacture procedure and to improve the yield by arranging a common monitor pattern for size measurement which is applicable to all pattern characteristics on a photomask substrate.

CONSTITUTION: A monitor chip area 1 is specified in the main chip area 3' of a wafer exposure area 2 and the monitor pattern for size measurement is arranged as a substitute for the main chip pattern of said area. In this case, a main chip is arranged in the area 3, and the area 1 is divided into four areas A and A', and B and B' to form high-density light shielding patterns. For example, size measurement light shielding patterns a1.a2Wf1.f2 which have, for example, about 50μm outward side length and are in different chevron shapes are formed at different intervals to high density. With regard to pattern width, a1=a2=12μm, and b1=b2=10μm; and c1=c2=8μm, and f1=f2=2μm. With regard to pattern intervals, a1Wa2=12μmWf1Wf2=2μm. Further, high-density light shielding patterns are formed in the A', B, and B' similarly.


Inventors:
MATSUI SHIYOUGO
Application Number:
JP17122082A
Publication Date:
April 06, 1984
Filing Date:
September 30, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L21/027; G03F1/00; G03F1/38; G03F1/44; G03F1/84; H01L21/30; (IPC1-7): G03F1/00; H01L21/30
Domestic Patent References:
JPS50116175A1975-09-11
JPS5640242A1981-04-16
JPS5396674A1978-08-24
Attorney, Agent or Firm:
Sadaichi Igita



 
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