Title:
LOOP ANALYSIS TESTING DEVICE FOR DIGITAL EXCHANGE SYSTEM
Document Type and Number:
Japanese Patent JPS60158759
Kind Code:
A
Abstract:
The present invention is an interconnection of a loop analysis test system (LATS) to a digital switching system. This arrangement includes the utilization of existing network units to establish a path connection from the computer of a LATS system to a measuring unit of the LATS system. This path through the digital switching system provides for the appropriate signaling requirements in order to simulate a telephone call to the digital switching system for connection to a subscriber. Another path is provided to connect the measuring unit to the subscriber line to be tested via a special access network. In addition, this arrangement includes a data base in the CPU switching system to provide for determining whether the connection of this path through the switching system is for a test access or for normal calling functions. The data base also records the interconnection of equipment such that the proper subscriber's line may be accessed when called by the LATS system.
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Inventors:
UIRIAMU AARU DANIERUZU
JIYON ESU YANGU
JIYON ESU YANGU
Application Number:
JP27351284A
Publication Date:
August 20, 1985
Filing Date:
December 26, 1984
Export Citation:
Assignee:
JII TEII II KOMINIYUKEISHIYON
International Classes:
H04M3/32; H04M3/30; (IPC1-7): H04M3/30
Attorney, Agent or Firm:
Motohiro Kurauchi
Previous Patent: JPS60158758
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