PURPOSE: To increase both the reliability and the processing capacity, by connecting plural serial bus loops of serial transfer system to which the CPUs are connected with other serial bus loops of serial transfer system via the inter-bus connecting devices.
CONSTITUTION: The CPU51W53 are connected to Y bus loops 54W56 via the CPU stations 63W65. The input/output devices 73W79 are connected to the Y bus loops 54W56, an X bus loop 57 and a Z bus loop respectively via the I/O stations 66W72. The loops 54W56 is connected to the loop 57 via the inter-bus connecting devices 59W61. The loop 57 is connected to the loop 58 via an inter- bus connecting device 62. The devices 73 and 74 have an access only by the CPU51, and the device 75 has an access only by the CPU52. An access is possible to the input/output devices 76W79 through any CPU.
NAKANISHI HIROAKI
OKADA MASAKAZU
MORIOKA TAKAYUKI
HARA HIDEYUKI
KASASHIMA HIROKAZU
OKA TOSHIHISA
| JPS477063A |