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Title:
LOGIC SIMULATION METHOD
Document Type and Number:
Japanese Patent JPH04114279
Kind Code:
A
Abstract:

PURPOSE: To exactly verify bus competition without error by providing an allowable time width storing means to store bus competition allowable time width set in advance and a competing state storing means to store a flag showing whether a bus is in a competing state at certain time during simulation or not.

CONSTITUTION: An allowable time width storing means 16 stores the allowable time width of bus competition designated to a bus to be the object of verification and is set in advance before starting the simulation. A competing state storing means 17 stores the flag showing whether the bus is in the competing state at certain time during the simulation or not, and sets a flag showing that all the buses are not in a verification state, before starting the simulation. An event possessing means 11 possesses one event at the current simulation time and decides whether the event is finished or not and when it is finished, an end processing is executed. Thus, the competition of the bus can be verified while considering the allowable condition.


Inventors:
SAKUMA HIROSHI
Application Number:
JP23479490A
Publication Date:
April 15, 1992
Filing Date:
September 05, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/25; G06F11/26; G06F17/50; (IPC1-7): G06F11/26; G06F15/60
Attorney, Agent or Firm:
Shin Uchihara



 
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