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Patent Searching and Data


Title:
MEMORY CHECK SYSTEM
Document Type and Number:
Japanese Patent JPS583200
Kind Code:
A
Abstract:

PURPOSE: To improve the reliability of check, by accumulating the number of the content of the same bit at the same bit location, calculating the accumulated value and collating the value with the check value.

CONSTITUTION: In checking a memory 2, 8-bit or B0W7 of each address in a program memory area 2a is read out altogether and stored in a register 3. A bit register 5 detects if the content of a specific bit in the register 3 is at "1" and outputs an addition signal S1 to an adder 6 only at "1". The adder 6 reads out a register 7 with the signal S1, adds "1" and stores the value to the register 7 as an accumulated value T. All the addresses are checked and outputted to a check circuit 9. The check circuit 9 reads out a check value stored in a check memory area 2b for collation. When the check value of each bit location and the value T are coincident, it is decided that the check value is correct.


Inventors:
YAMAMOTO MASAMI
INAMORI SHIYUUHEI
Application Number:
JP10285381A
Publication Date:
January 08, 1983
Filing Date:
June 30, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F12/16; G06F11/00; (IPC1-7): G11C29/00
Domestic Patent References:
JP35000662A
JPS541422A1979-01-08
Attorney, Agent or Firm:
Koshiro Matsuoka