PURPOSE: To realize size reduction, profitability, and high reliability by using only a read-only memory stored with necessary count data and control data in respective addresses.

CONSTITUTION: Count data 2n is stored in addresses 4n and 4n-2 (n denotes an integer ≥1) of the read-only memory 6, count data 2n-1 is stored in addresses 4n-1 and 4n-3, and count data 0 is stored in an address 0. Further, count data stored in an address 4m-2 (m<n) is changed into the count data 0 and the binary count data terminals D0WD2 of the memory 6 are connected to data terminals A1WA3 which are one digit higher; and a circuit which counts (m) periods of a clock signal inputted to an address terminal 0 is provided. Control data is added to each count data and control data are outputted from control terminals D3 and D4 together with corresponding count data outputted in the counting process of the counting circuit, so control pulses of necessary time-series codes are generated.