PURPOSE: To enable the writing and erase of a memory of a single MNOS type transistor at an arbitrary position in a memory-array by using one N channel (P) MNOS type transistor, two P channel (N) MOS transistors and a memory matrix using a P(N) conductive well as a unit cell.

CONSTITUTION: The potential VX3 of a P well 25 containing the MNOS type transistor 39a to which writing is to be executed is made lower than V0, and the state of a reverse bias is brought between a substrate and the P well. Potential VY1, VY4 equal to VX3 or higher than VX3 is each applied to a Ys electrode and a Yd electrode connected to the MNOS type transistor 39a, potential sufficiently higher than VX3, VY1, VY4 is applied to an X1 electrode 23 connected to the source of the first MOS transistor 37a in the same unit cell as the MNOS type transistor, the potential is applied to the gate electrode of the MNOS type transistor 39a, electrons are injected into the gate insulating film of said MNOS type transistor, and the memory is written. When voltage sufficient for discharging electrons is applied to the gate insulating film of the transistor 39a, the memory only of the single MNOS type transistor is erased.