Title:
JOSEPHSON INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5853874
Kind Code:
A
Abstract:
PURPOSE:To prevent breakage of control line by inverting the layout location of a ground plane and control line sandwiching a Josephson junction. CONSTITUTION:A base electrode 4, tunnel insulating film 5 and counter electrode 6 are formed through the dielectric layer 27 on the control line 28 formed on an Si substrate 1, and a ground plane 22 such as Nb etc. is also formed through a dielectric layer 23 over the entire part of substrate. In this structure, the surface step of the upper most layer is fantastically reduced as compared with the control line and probability of breakage of wiring is reduced. Moreover, this Nb layer 22 is used also in common as the ground plane of second layer and the Josephson junction element of second layer is provided with the upper layer of control line as in the case of existing device. In this case, since the control lines of both first and second layers are not sandwiched by a pair of ground planes and therefore, a current IH of control lines flows into only the plane opposing to the Josephson junction element, and the sensitivity in IC of two layers is improved and the sensitivity of elements on each layer can be equalized.
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Inventors:
SHIBAYAMA HIKOSUKE
Application Number:
JP15268281A
Publication Date:
March 30, 1983
Filing Date:
September 26, 1981
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L39/22; H01L27/18; (IPC1-7): H01L39/22
Domestic Patent References:
| JPS5350986A | 1978-05-09 |
Attorney, Agent or Firm:
Seiichi Samukawa