Title:
TEST FACILITATING SYSTEM FOR LSI
Document Type and Number:
Japanese Patent JPS6041237
Kind Code:
A
Abstract:
PURPOSE:To enable to test by an inexpensive tester by adding a hardware of small capacity to a control pin and the interior of an LSI for facilitating the test, thereby facilitating the test. CONSTITUTION:In a test of an LSI21 to be measured by a performance board 23 and a tester body 22, a control pin PC1 is added to facilitate the test to the LSI21. This pin is connected to an additional circuit (gate 213), and the circuit 213 controls try state buffer group 211, 212 disposed at the final stage of the LSI21. In other words, the circuit 213 sets one group of output buffer group to a high impedance state by a level signal coming through the pin PC1 to perform a test of each group in twice test sequences.
Inventors:
SATOU KAZUYUKI
Application Number:
JP14940983A
Publication Date:
March 04, 1985
Filing Date:
August 16, 1983
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
G01R31/26; G01R31/28; G01R31/317; G01R31/20; G01R31/3185; H01L21/66; H01L21/822; H01L27/04; (IPC1-7): G01R31/20; G01R31/26
Attorney, Agent or Firm:
Takehiko Suzue