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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JPS6010754
Kind Code:
A
Abstract:
PURPOSE:To pick up an impurity diffusion layer internally formed on the surface of substrate through a fine potential transfer channel by a method wherein an insulating thin film is provided on the interface of substrate of a pierced hole made on the substrate extending from the surface of the first conductive type semiconductor substrate to the second conductive type impurity layer to fill the hole with conductive material. CONSTITUTION:A p type silicon substrate 1 is implanted with n type impurity ion from surface to inside to form an n<+> type diffusion wiring layer 2 after activation and firstly growing an SiO2 film 3 on the surface of oxidized substrate 1, an expected hole piercing part forms an opened resist pattern 4. Then the SiO2 film 3 is selectively removed by means of etching process utilizing the resist pattern 4 as a mask and the silicon substrate 1 is selectively removed to make a pierced hole 5 with the bottom reaching the wiring layer 2. Secondly, after removing the resist pattern 4, an oxide film 6 is grown on the side walls and bottom of the pierced hole 5 by means of thermal oxidation. Then an n<+> diffusion layer 2 is exposed on the bottom of the pierced hole 5 by means of removing the part of oxide film 6 on the bottom of the pierced hole 5 leaving an oxide film 6' on the interface with the substrate 1 of said pierced hole 5. Finally the pierced hole 5 formed of the oxide film 6' is filled with n<+> type polycrystalline silicon.

Inventors:
MIZUTANI YOSHIHISA
Application Number:
JP11936783A
Publication Date:
January 19, 1985
Filing Date:
June 30, 1983
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
H01L23/52; H01L21/28; H01L21/3205; H01L29/41; (IPC1-7): H01L21/88; H01L21/28
Attorney, Agent or Firm:
Takehiko Suzue