PURPOSE: To eliminate the counting error of a multi-stage counter circuit, by using a D flip-flop to eliminate the generation of a pulse having a pulse width below a specified value.

CONSTITUTION: The DFF21 using an inverting signal of a pulse CLK as a clock input is inserted to a counter circuit which receives the clock pulse CLK synchronized with a pulse PLS2, and asynchronous pulse signals PLS1, 2 and counts the number of the pulse CLK outputted between the leading of the signals PLS1 and PLS2. Since the point of time of the leading of the signal PLS1 is synchronized with that of the pulse CLK with the DFF2, the pulse having a pulse width below the specified value is not generated at the start of counting of the pulse CLK and no counting error of the multi-stage counter circuits C1, C2 and Cn occurs.