Title:
MULTIPLEX PROCESSOR TYPE CONTROLLER AND INPUT FILTER
Document Type and Number:
Japanese Patent JPS5975304
Kind Code:
A
Abstract:
The present invention includes a plurality of input/output processors communicating with a master processor. Each of the input/output processors has a filtering mechanism to filter the inputs before transmission to the master over the communication channel precluding the necessity of filtering at the master. More importantly, the shared communications system is not loaded down with every change of an input. Because of this feature, only meaningful changes are put on the communication line, thus substantially reducing its load which makes its effective response time stay high. The inputs when received at the master can be immediately handled to improve the central processor response time. Two types of filtering are provided, in particular, transition and debounce filtering to respond to switch and sensor inputs. Also, there is provided a means to programmably select the type of filter and the time period of filtering.
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Inventors:
ANSONII MAIKERU FUEDERIKO
AANESUTO RII REGU
SUCHIIBUN PII UIRUTSUETSUKU
HAARI KISHIYOOA PURASADO
JIEIMUZU JIYOSEFU PETORII
AANESUTO RII REGU
SUCHIIBUN PII UIRUTSUETSUKU
HAARI KISHIYOOA PURASADO
JIEIMUZU JIYOSEFU PETORII
Application Number:
JP16906983A
Publication Date:
April 28, 1984
Filing Date:
September 13, 1983
Export Citation:
Assignee:
XEROX CORP
International Classes:
G05B15/02; G05B19/05; (IPC1-7): G05B15/02
Domestic Patent References:
| JPS56114002A | 1981-09-08 | |||
| JPS5436732A | 1979-03-17 | |||
| JPS5217979A | 1977-02-10 | |||
| JPS5412177A | 1979-01-29 |
Attorney, Agent or Firm:
Minoru Nakamura