Title:
IMPURITY DIFFUSION INTO SEMICONDUCTOR CRYSTAL
Document Type and Number:
Japanese Patent JPS5918631
Kind Code:
A
Abstract:
PURPOSE:To avoid generation of crystal defect based on rough surface generated during diffusion by using a mask as thin as allowing impurity to transmit therethrough at the diffusion area and executing thermal processing under the impurity element ambient on the occasion of diffusing impurity to the local areas of semiconductor crystal of which surface is covered with a cap layer which includes an element in saturated vapor pressure. CONSTITUTION:An N type InP buffer layer 2, an InGaAsP active layer 3, a P type InP clad layer 4, an N type InGaAsP cap layer 5 and a non-doped or N type InP mask layer 6 are stacked on an N type InP substrate 1 and these are caused to grow. Next, an SiO2 insulating layer 7 is deposited on the layer 6, a window is opened and a thin area of layer 6 is formed within the aperture using an etchant which is composed of sulfuric acid, hydrogen peroxide and water shows excellent etching rate. Thereafter, the layer 7 is removed a P type impurity is diffused until it enters the layer 4 with the partial thin layer 6 used as the mask. Thereby, the desired region 8 can be obtained.
Inventors:
ISODA YOUICHI
Application Number:
JP12793382A
Publication Date:
January 31, 1984
Filing Date:
July 22, 1982
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L21/22; H01L21/223; H01S5/00; (IPC1-7): H01S3/19
Attorney, Agent or Firm:
Uchihara Shin