Title:
MOUNTING STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5821350
Kind Code:
A
Abstract:
PURPOSE:To contrive the reduction of mounting costs and the rationalization of processes, by pinching an adhesion layer wherein conductive particles are mixed between a wiring substrate having lead wires and an IC chip having many junction pads. CONSTITUTION:Au balls with diameters approx. 15mum are sufficiently mixed in an epoxy resin being printed on the wiring substrate 5. The printing thickness, when the IC chip 7 is phases down, is formed to the degree that Au balls are not superposed in a thickness direction, and Au balls are mixed in a quality to the degree that they hardly contact the adjacent balls. Thereat, the junction pad 8 of the IC chip is electrically connected to the lead wire 6 on the wiring substrate 5 via the Au ball. It is preferable that the Au ball with the diameter 15mum is contained in a pad area with one side 100mum in five or more. Further, when pressing on hardening by using a resin which contracts in volume after hardening, or when connecting to an Al pad by using particles wherein particles of In or Sn are gilt, the loading can be performed to an extreme high reliability, and the positioning is unnecessary. In this constitution, mounting processes are rationalized resulting in cost reduction.
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Inventors:
OGUCHI KOUICHI
Application Number:
JP11959581A
Publication Date:
February 08, 1983
Filing Date:
July 30, 1981
Export Citation:
Assignee:
SUWA SEIKOSHA KK
International Classes:
H05K3/32; H01B1/00; H01B1/22; H01B5/00; H01B5/16; H01L21/56; H01L21/60; (IPC1-7): H01L21/60; H05K3/32
Attorney, Agent or Firm:
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