PURPOSE: To attain ease of circuit integration by constituting a coefficient device and an adder with a switched capacitor and an operational amplifier and constituting also a delay circuit similarly.
CONSTITUTION: A sample-and-hole stage 10 comprising capacitors C10∼12, switches S11, 12 and an operational amplifier (OPAmp) O10 samples and holds sequentially an analog signal and outputs it. An input signal is fed to a capacitor C12 through the switch S12. On the other hand, an output signal is fed to a capacitor C11 via the switch 11. Thus, an electric charge stored in the timing CL1 is fed to an inverting input of the OPAmpO10 at the same time at a point of time of a clock timing CL3. Further, the OPAmpO10 acts like a load feedback amplifier and an output voltage cancelling the electric charge of the capacitors 10∼12 across the capacitor C10 in proportion to the sum of the electric charges in the capacitors 10∼12. A delay stage 20 fetches a signal of a pre-stage to a capacitor C21 in the timing CL1. Coefficient stages 40, 50 and 60 change the amplitude gain of the output signal. Further, capacitors C72∼74 are connected to the inverting input of an OPAmpO70 in the timing CL3 at the same time in an adder stage 70 and an output signal being the sum is obtained.
YAGI SHIZUO
MATSUMOTO SHIYUUZOU
