PURPOSE: To attain high speed operation without attending generation of malfunction due to slow operating speed of an AND array by separating the operation of the AND array and the operation of an OR array.

CONSTITUTION: An input signal is inputted to the AND array 1 from an input register 3 at a time I , and the operation of the AND array 1 is executed between times I and II. A signal of the AND array 1 is inputted to a flip-flop circuit (FF)5 at the time II and stored therein. When the next signal is inputted to the AND array at a time III, the signal stored in the FF5 is inputted to the OR array 2 and the operation of the AND array 1 and the operation of the OR array 2 are executed at the same time between times III and IV. Further, the next output signal of the AND array 1 is inputted to the FF5 at the time IV, an output signal is outputted from an output register 4 at a time V, and the signal is inputted from the input register 3 to the AND array 1 at the same time and the signal is inputted to the OR array 2 from the FF5.