PURPOSE: To improve the through-put of a device, by providing a storage means and an analysis means to the same machine instruction as a CPU for an additional operation device.

CONSTITUTION: When a machine instruction is stored in a machine instruction register 15' of an execution unit 15, the same machine instruction is stored in its machine instruction register 201 even at an additional operation device with the same machine cycle and interpreted independently entirely. When this machine instruction is a machine instruction which can be processed with the additional operation device only, a sequence control section 207 is controlled with the result of analysis of the machine instruction of the register 201 in the next machine cycle and the microprogram sequence on a control storage 208 is started. On the other hand, at the CPU the microinstruction picking up the next machine instruction is executed in this machine cycle when the instruction can be executed at the additional operation device only. As a results, parallel processing control between the two devices can be simplified and the operation start time of the additional operation device to the machine instruction can be quickened.