PURPOSE: To reduce fluctuation in the threshold voltage due to variance among load FETs by connecting a D type MOSFET of the same conduction type with a load FET to the input stage of an inverter which uses the D type MOSFET as a load resistance in series.

CONSTITUTION: The input stage consists of enhancement MOSFETs Q1 and Q2 connected to a power source voltage Vcc and an earth point respectively and a depletion type MOSFETQ5 connected between the MOSFETs Q1 and Q2, and the output stage consists of a depletion type MOSFETQ3 and an enhancement type MOSFETQ4 which are connected together in series. When a signal having a higher level than a normal input signal is supplied to an input terminal 1, the MOSFETQ4 turns on to generate a low-level output and a test circuit, etc., in an LSI are put in operation. Then, fluctuation in th threshold voltage of the MOSFETQ3 is compensated by the MOSFETQ5 formed in the same process to nearly equalize it to the threshold voltage of the circuit.