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Title:
SIGNAL FETCHING DEVICE
Document Type and Number:
Japanese Patent JPS589427
Kind Code:
A
Abstract:

PURPOSE: To eliminate effectively the AC noise for an analog input signal fetching device which performs an A/D conversion, by using a clock pulse signal which sets the time of integraion of an integral A/D converter at an integer- fold value of the power supply frequency and at the same time setting the cycle of the AC signal used to an input circuit at a fraction of an integer of the time of integration.

CONSTITUTION: The analog input signal supplied to an input terminal 1 is fetched by an input circuit 2 and integrated for a prescribed time by an integral A/D converter 4 which is insulated by an isolator 3 to be converted into a digital signal. This digital signal is delivered through a terminal 5. The frequency of a power supply AC which actuates each part of the circuits 2∼4 is detected by a detector 6. A frequency divider 81 produces a clock pulse signal so as to set always the time of integration of the converter 4 at an integer-fold value. The output pulse of the divider 81 is divided furthermore, and a driving signal of a fraction of an integer of the integration time of the converter 4 is supplied to the circuit 2.


Inventors:
HARUHARA FUSHIAKI
Application Number:
JP10738881A
Publication Date:
January 19, 1983
Filing Date:
July 09, 1981
Export Citation:
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Assignee:
CHINO WORKS LTD
International Classes:
H03M1/52; H03M1/08; (IPC1-7): H03K13/20
Domestic Patent References:
JPS53115162A1978-10-07



 
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