Title:
VECTOR PROCESSOR
Document Type and Number:
Japanese Patent JPS6027070
Kind Code:
A
Abstract:
PURPOSE:To store the element trains of all arithmetic results to a main memory with generation of an arithmetic error by inhibiting generation of an interruption of arithmetic error when said interruption is produced. CONSTITUTION:When an arithmetic error is produced, a microprogram control part 15 sets an FF22 to close an AND gate 21. This inhibits to deliver an arithmetic error signal ERROR to the part 15 as an arithmetic error interruption signal INT. As a result, no arithmetic error interruption is produced and the operation is continued regardless of the arithmetic error signal given from an operator. When the operation is through with all elements, the arithmetic results so far written to a vector register are shifted to a main memory. Therefore the approximate value is set in an arithmetic error mode with a cumulative operation, for example, and therefore the final result is relieved.
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Inventors:
SAKATA KUNIHIKO
Application Number:
JP13540283A
Publication Date:
February 12, 1985
Filing Date:
July 25, 1983
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
G06F9/22; G06F15/78; G06F17/16; (IPC1-7): G06F9/22
Attorney, Agent or Firm:
Takehiko Suzue