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Patent Searching and Data


Title:
PEAK VOLTAGE DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPS5957171
Kind Code:
A
Abstract:

PURPOSE: To obtain a small peak voltage detection circuit with a large time constant using an IC by controlling constant at discharge according to a DC current amplification factor of a transistor.

CONSTITUTION: When the voltage of an input terminal 10 exceeds the voltage of the output terminal 11, current flows through to a current mirror circuit made up of transistors TRQ2 and TRQ5, Q6 and Q9, a load resistance and the like whose saturation is prevented with a transistor (TR)Q1 and a clamping transistor TRQ11 according to the peak voltage. Then, with the on-control of a transistor TRQ3, a capacitor C is charged according to the peak voltage. Subsequently, when the voltage of the terminal 10 drops, the transistor TRQ3 is turned OFF and the capacitor C is discharged with a large time constant corresponding to the product of the resistance value of a resistance R5, a DC amplification factor of a transistor TRQ4 connected in series thereto and the capacitance value of the capacitor C to lower the output voltage of the terminal 11. This provides a small peak voltage detection circuit with a large time constant using an IC.


Inventors:
SAKURA NARIYUKI
YAMADA HISASHI
Application Number:
JP16761282A
Publication Date:
April 02, 1984
Filing Date:
September 28, 1982
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
G01R19/04; (IPC1-7): G01R19/04
Attorney, Agent or Firm:
Norio Ogo (1 outside)