PURPOSE: To simplify the hardware of a computer system by outputting an interruption instruction code written previously to a register onto a bus when transmitting an interruption request signal to a CPU and receiving an interruption permission signal.

CONSTITUTION: A writable register is provided in an IC device (LSI) for peripheral interface, and an interruption instruction code is written previously to said register from a CPU9. When an interruption condition is generated at an input/ output device 10, the LSI8 feeds an interruption request signal IRQ to the CPU9. Receiving an interruption permission signal INTA from the CPU9, the LSI8 feeds the interruption instruction code written to the register to the CPU9 via a bus line. Thus an interruption instruction code, e.g., a restart instruction is fed to the CPU9 for execution of the interruption processing.