PURPOSE: To form a semiconductor memory circuit with a wide operation margin by controlling the gate voltage of the transistor (TR) of a pull-up circuit and the gate voltage of the TR of a pull-down circuit by a rise and fold in source voltage.

CONSTITUTION: A switching TRQ12 which turns on when the source voltage VDD drops and turns off when rising is provided, and a switching TR which has the opposite characteristics to power source variation of a switching TRQ13 that turns on when the source voltage drops and turns off when rising is provided. Only the pull-up circuit which includes the TRQ12 is operated to a power source drop to prevent a drop in VREF due to the power source drop. Further, only the pull-down circuit which includes the TRQ13 is operated to a power source rise to prevent a rise in VREF due to the power source rise. Then, variation in VREF is minimized within some range of the typical value (TYP) of the in-use source voltage VDD.