Title:
INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS594140
Kind Code:
A
Abstract:
PURPOSE:To eliminate the deterioration in characteristics of the integrated circuit device when a multilayer metal wiring is used and to contrive improvement in the yield rate and quality of said device by a method wherein a silicon nitride film is formed as an interlayer insulating film after aluminum oxide has been covered around the aluminum of the first wiring layer. CONSTITUTION:Diffusion layers 12, 12' and 12''' are formed on a silicon substrate 11, and an MOS type transistor having a polycrystalline silicon 13 as a gate electrode is formed. Aluminum is vapor-deposited, the part other than an aluminum wiring 15 is removed by performing an etching, and an aluminum oxide 16 is covered around the aluminum layer using an anodic formation method. Besides, a silicon nitride film 17 of 1.0mum in thickness is formed by performing a plasma vapor-phase growing method, and after an aperture for electrode has been provided, aluminum of 1.0mum in thickness is coated by performing a vacuum evaporation method, and the second aluminum wiring 18 is formed by removing the aluminum using a photolithographic method. As the layer 15 is covered with the aluminum oxide 16, the injection of electric charge from the layer 15 into the film 17 is extremely reduced, thereby enabling to prevent the deterioration of characteristics caused by parasitic transistor effect.
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Inventors:
YAMANAKA TAKASHI
Application Number:
JP11319582A
Publication Date:
January 10, 1984
Filing Date:
June 30, 1982
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L23/522; H01L21/31; H01L21/314; H01L21/768; (IPC1-7): H01L21/314
Attorney, Agent or Firm:
Uchihara Shin
Next Patent: JPS594141