Title:
DURAL PATH BUS CONSTRUCTION FOR MUTUAL CONNECTION OF COMPUTER
Document Type and Number:
Japanese Patent JPS5941031
Kind Code:
A
Abstract:
A bus structure for use in a computer network requiring high availability and reliability of communications. Multiple bus paths (2A, 2B) are provided. When a transmission is to be made, under most circumstances the path is selected at random, with all paths being equally probable. Thus, failure of a path is detected quickly. Each host device in the network connects to the bus paths through an interface, or port (1). The task of path selection is carried out by the ports, independently of the host devices. The ports also detect path failures and automatically switch over to an alternate good path upon detection of such a failure, all without host involvement. Virtual circuit communications between hosts are transparent to path selection and switching, so the only indication to a host device of a path failure is a decrease in throughput. Most of the signal processing apparatus of each port (10, 20A, 20B) is shared by the paths, only one path being supported at any given time. Thus, the addition of a second bus path involves only minimal cost.
Inventors:
UIRIAMU DEI SUTORETSUKAA
DEIBUITSUDO SOMUPUSON
RICHIYAADO KASABONA
DEIBUITSUDO SOMUPUSON
RICHIYAADO KASABONA
Application Number:
JP7919683A
Publication Date:
March 07, 1984
Filing Date:
May 06, 1983
Export Citation:
Assignee:
DIGITAL EQUIPMENT CORP
International Classes:
G06F15/16; G06F11/20; G06F11/22; G06F13/36; G06F13/38; G06F13/40; (IPC1-7): G06F3/00; G06F15/16
Domestic Patent References:
| JPS56114063A | 1981-09-08 | |||
| JPS5629731A | 1981-03-25 | |||
| JPS5552130A | 1980-04-16 | |||
| JPS5057347A | 1975-05-19 | |||
| JPS5463634A | 1979-05-22 | |||
| JPS5513475A | 1980-01-30 |
Attorney, Agent or Firm:
Minoru Nakamura
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