PURPOSE: To bring the circuit into the synchronization state automatically within a time being nearly twice the maximum time required for the synchronization and to eliminate the need for a troublesome operation by inverting the phase of an input clock automatically after a prescribed time when a leading edge of the input clock stays in a dead zone of an input pattern.

CONSTITUTION: When a pattern synchronization establishing signal 27 is missing, a one-shot circuit 32 is triggered and the one-shot circuit 32 outputs a pulse having a time width larger than the maximum time required for establishing synchronization, and the pulse and the pattern synchronization establishing signal 27 are inputted to an OR circuit 29. A T flip-flop 34 is triggered by an output edge of the OR circuit 29 at the trailing edge of the output pulse of the one-shot circuit 32 in the asynchornizing state, the output is fed to an inverting circuit 35, which inverts the input clock fed to a retiming circuit 15 in response to the output of the T flip-flop 34. Thus, the adjustment of a variable delay circuit is not required to simplify the 7 operation and to save the time.