PURPOSE: To attain high speed fault detection, by branching and processing a frame header received from an upperstream station and sending the received frame header as it is to a lowerstream station in a timing of sending a frame.

CONSTITUTION: When frame synchronization is established by an FH detection circuit 2 and a frame synchronization protection circuit 4, a data 62 sent from an upperstream station is decoded by an S/P conversion circuit 1 and a decoding circuit 10. A frame header FH61 is sent to a selector 12 and linked with a decoded data 62 and the result is sent to a data processing section 5. When a frame transmission request signal is inputted to a transmission timing generating circuit 6 from the processing section 5 the header 61 is inputted to the selector 8 the data 62 inputted next to the header 61 is sent to a lowerstream section by a coding circuit 11 and a P/S conversion circuit 9 as a serial data.