PURPOSE: To form a bipolar N-P-N transistor for an output circuit simultaneously to a COMS integrated circuit chip without adding special processes by implanting the ions of boron by acceleration energy and using a process selectively forming a buried type intermediate concentration P type region.

CONSTITUTION: First and second N wells 2, 7 are formed in a P type silicon substrate 1, and N+ diffusion layers 9, 10 are formed together with the N+ layer 4 of the source-drain of the N channel MOS transistor of a CMOS. An active base 11 of the N-P-N transistor is formed through the same process as one in case of the formation of the intermediate concentration P type region 5 of the N channel MOS transistor. An inert P+ region 8 for surrounding the emitter region 10 is formed together with a P+ region 3 of the source-drain of a P channel MOS transistor in the first N well 2, and the P+ region 8 is formed through the ion implantation of boron and the N+ region 10 through the ion implantation of arsenic. The P+ region 8 is formed in depth deeper than the N+ region 10 because boron is implanted down to a section deeper than arsenic.