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Title:
PROGRAM LOAD SYSTEM
Document Type and Number:
Japanese Patent JPS60102041
Kind Code:
A
Abstract:

PURPOSE: To eliminate the need for a long time for program load by dividing a program to be loaded, assigning a lead wire or a channel to each of each part and performing it in parallel with the program load.

CONSTITUTION: A main controller 2-1 is connected to plural slave controllers 2-2, 2-3 via a time division multiplex highway outgoing line 2-4 and an incoming line 2-5. One channel is assigned among the controllers 2-1, 2-2 and 2-3 and other plural channels (not shown) are assigned to general terminal devices. A program of a memory 2-7 is divided into N (in the figure N=4) by a microcomputer 2-6 as No.0∼No.3, four highways are occupied via a highway interface 2-8, transmitted in parallel with the slave controllers 2-2, 2-3 and stored in the memory section 2-7 via each highway interface 2-8. Thus, the time required for the program load is decreased to 1/4.


Inventors:
MORITA TAKASHI
AMADA EIICHI
Application Number:
JP20906883A
Publication Date:
June 06, 1985
Filing Date:
November 09, 1983
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F15/177; (IPC1-7): H04L11/00
Attorney, Agent or Firm:
Akio Takahashi



 
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