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Patent Searching and Data


Title:
INSTRUCTION DECODER
Document Type and Number:
Japanese Patent JPS6133542
Kind Code:
A
Abstract:

PURPOSE: To assign plural instructions to one instruction code by decoding an instruction code in accordance with an instruction code and the output of an internal storage means.

CONSTITUTION: A control circuit 40 specifies an address storing the instruction code of the next instruction to be executed to a memory 30 through a memory control line 90 and outputs the instruction code stored in the address to a bus 50. The control circuit 40 latches the instruction code on the bus in a decoder 10 through a decoder control line 100. The decoder 10 decodes the instruction code to recognize the instruction (PX instruction e.g.). When an output of an FF20-1 is "0", the PX instruction is decoded by the decoder 10 as a PUSH instruction to command the PUSH instruction. At that time, the FF20-1 is inverted to "1". Therefore, the succeeding PX instruction is decoded by the decoder 10 as a POP instruction.


Inventors:
DOI KOJI
Application Number:
JP15611284A
Publication Date:
February 17, 1986
Filing Date:
July 26, 1984
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F9/22; G06F9/30; (IPC1-7): G06F9/22; G06F9/30
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)