Title:
PHASE SYNCHRONIZING LOOP
Document Type and Number:
Japanese Patent JPS60158726
Kind Code:
A
Abstract:
A phase-locked loop capable of generating a plurality of stable frequency signal. This loop includes a plurality of voltage controlled oscillators which are sequentially coupled to the output of a phase sensitive detector by a multiplexer.RF switches then sequentially couple, in synchronism with the multiplexer, the oscillator outputs to a programmable divider which, in turn, is coupled to an input of the phase sensitive detector, the other input thereto being coupled to a reference oscillator. The dividing factors for the programmable divider are inputted thereto, in synchronism with the multiplexer, from a memory.
Inventors:
DAGURASU JIYON HATSUCHI
JIEFURII RII KOTSUKUSU
JIEFURII RII KOTSUKUSU
Application Number:
JP28198384A
Publication Date:
August 20, 1985
Filing Date:
December 26, 1984
Export Citation:
Assignee:
PHILIPS CORP
International Classes:
H03L7/16; H03L7/14; H03L7/18; H03L7/199; (IPC1-7): H03L7/16; H03L7/18
Attorney, Agent or Firm:
Akihide Sugimura
Previous Patent: JPS60158725
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