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Patent Searching and Data


Title:
MIS TYPE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS6098674
Kind Code:
A
Abstract:

PURPOSE: To remove charges induced in the part of a MIS type transistor in an ROM by conventional annealing by a method wherein the adjacent parts of gate oxide films are formed to a thick oxide film having approx. the thickness of a field oxide film.

CONSTITUTION: An N+ diffused region 3 and N+ diffused regions 41∼44 serving as the source and drain of an MNOS type transistor are formed in a P- well 2. On the surface of the well, gate oxide films 61∼63 are formed by adjacency in the gate region of the MIS type transistor, and thick oxide films 10 of the same thickness as that of the field oxide film 5 are formed at the adjacent parts between these oxide films 61∼63. An SiN film 7 is formed on the films 5 and 6, and an electrode wiring metal 8 is formed theron in a required pattern. Such a construction facilitates hydrogen diffusion in the presence of the films 10.


Inventors:
ICHIKAWA YOUICHI
Application Number:
JP20490683A
Publication Date:
June 01, 1985
Filing Date:
November 02, 1983
Export Citation:
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Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
H01L29/78; (IPC1-7): H01L29/60
Attorney, Agent or Firm:
Hiroshi Kikuchi