PURPOSE: To simplify each program constitution by providing an FIFO (first-in first-out) memory to an input device of plural microprocessors to write and read signals to the memory independently thereby attaining loose coupling to processors.

CONSTITUTION: In transmitting a signal from a maintenance processor OMP to a call processing processor CP, the processor OMP transmits an address ADRS write control signal CTL and a 8-bit write data DATA to the own maintenance write control circuit M-WTC. The circuit M-WTC stores temporarily the data, transmits a write control signal WC and a write data WDATA to the FIFO memory C-FIFO of 64 words of a processor LP, and the data are written in the memory C-FIFO. The processor CP looks into periodically the own FIFO memory and reads a data if it exists. The signal is transmitted from the processor OMP to the CP in this way and the system processes similarly in case of the reverse data transmission.