Title:
INSPECTING SYSTEM FOR SEMICONDUCTOR CHIP
Document Type and Number:
Japanese Patent JPS584937
Kind Code:
A
Abstract:
PURPOSE:To improve detecting accuracy and to shorten inspection time without resorting to visual inspection by a method wherein a scanning line, set up near the place of wire pressure attaching, senses wire bonding conditions, and monitors specifically the neck shaped sections, frequented by line disconnections, and the deviation of wire attaching locations, when wires are bonded to a semiconductor chip. CONSTITUTION:A semiconductor chip 2 is stuck on a platform 1 provided with pads 3 and 4 which in turn are connected to a terminal installed on said chip 2 with a very thin wire 5. Next, an image pickup device 7 with a lens system 6 is arranged facing the bonding position and is activated by a driving circuit 8 for the monitoring of the bonding work. That is to say, the image signal outputted by the circuit 8 is displayed on the output unit 16 after passing an image signal binarizing pre-processing circuit 9, a memory 11, a scanning line setting circuit 13, and a wire disconnection detecting circuit 15. During this period, a controlling circuit 10 connected to the driving circuit 8 monitors and regulates the circuits 8, the output unit 16, and the each unit connected thereto. This provides automatic monitoring of the bonding process.
Inventors:
MIYAMURA MASATO
NAKAJIMA MASAHITO
HIZUKA TETSUO
NAKAJIMA MASAHITO
HIZUKA TETSUO
Application Number:
JP10290881A
Publication Date:
January 12, 1983
Filing Date:
June 30, 1981
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H01L21/66; H01L21/60; (IPC1-7): H01L21/60
Attorney, Agent or Firm:
Koshiro Matsuoka
Next Patent: WIRE BONDING SYSTEM